====== LC //e Card - I/O Addresses ======

===== $C000-$C07F =====

Locations with undefined reads in the $C000-$C07F range tend to return the last key pressed.

^ Address ^ R/W ^ Use ^
| $C028   | R/W | Switch to main firmware (undocumented). |
| $C029   | R/W | Switch to alt firmware bank (undocumented). |
| $C02B   | R/W | Bits in table below.* |
| $C05C   | R   | Bit 2 = speed selected in option panel (1=fast).* |
| $C072   | W   | The firmware (Int CX ROM and PFI) write either $5A or $00 here.%%**%% |

%%*%% See [[http://www.1000bit.it/support/manuali/apple/technotes/aiie/tn.aiie.10.html|TN.AIIE.10]].

%%**%% Writes to $C072:

^ Who    ^ Where ^ Value ^
| INT CX | $C4AB | $00 |
| INT CX | $C579 | $5A |
| PFI 0  | $D445 | $5A |
| PFI 0  | $D470 | $00 |
| PFI 0  | $F5EF | $00 |
| PFI 0  | $F60B | $5A |
| PFI 1  | $D4BC | $5A |
| PFI 1  | $D519 | $00 |
| PFI 1  | $F178 | $5A |
| PFI 1  | $F205 | $00 |



==== $C02B Bits ====

^ Bit ^ Use ^
| 7   | Set in IRQINTCX |
| 6   | Cleared at $C41C in Int. CX ROM, set at $C573 |
| 5   | Enable writes to some areas of the $C8xx space? |
| 4   | Enable a second aux RAM bank? |
| 3   | Set Alt FW Bank, 0=D1, 1=D2. |
| 2   | Set CPU speed (1=fast). Documented. |
| 1   | 3.5%%"%% signal: HDSEL |
| 0   | 3.5%%"%% signal: /3.5DISK |

The PFI code always sets bits 4 and 5 after storing $5A into $C072, and always clears bits 4 and 5 after storing a zero into $C072.  This appears to enable writing to $C8-space and to a second aux bank.


===== Slots =====

==== Clock Card ====

The clock card has the following in it's I/O locations most times:

^ Offset ^ Dir ^ Use ^
| 00    | R/W | Firmware writes here, perhaps as a control register, the value written here is readable |
| 01    | R   | Reading this location continuously returns the date and time in the ThunderClock format |
| 02    | ?   | Unknown (always $FF?) |
| 03    | R   | The firmware uses this location |
| 04-07 | R   | Some kind of counter, seems to always be 7 more than the 08-0E value |
| 07    | R   | A different counter value |
| 08-0E | R   | Yet another counter value |
| 0F    | R   | And we have another counter |

Changing the date/time in the Macintosh control panel while the %%//%%e is running causes the 01 offset value to return continuous 8D (CR).  The firmware is able to fix this, but I haven't figured out how, yet.

The characters out of the 01 offset are msb off, except for the CR value.