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mg_notes:iie_card:mac_side_interface [2019/08/14 15:19]
M.G. ↷ Page moved from ​mg_note:iie_card:mac_side_interface to ​mg_notes:iie_card:mac_side_interface
mg_notes:iie_card:mac_side_interface [2019/10/14 04:01] (current)
M.G.
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 Each has 16 bits of usable data in big-endian order. ​ Therefore the high byte is at the register+0 address, low byte at the register+1 address. Each has 16 bits of usable data in big-endian order. ​ Therefore the high byte is at the register+0 address, low byte at the register+1 address.
  
-^  ^  Read  ^^  Write  ^^^+^  ^  Read  ^^  Write  ^^  ^
 ^  Register ​ ^  High  ^  Low  ^  High  ^  Low  ^ Notes ^ ^  Register ​ ^  High  ^  Low  ^  High  ^  Low  ^ Notes ^
 |  $00  |  Trap Code  ||  None  || 0 when not trapped, trap code otherwise | |  $00  |  Trap Code  ||  None  || 0 when not trapped, trap code otherwise |