Apple IIc Plus MIG Chip

The MIG is a custom chip in the Apple IIc Plus that provides signals for accessing 3.5" disk drives and access to a 2K static RAM chip mainly used to buffer 3.5" sector data for reading and writing. The RAM is also used for the accelerator.

MIG Chip

Pins/Signals

According to the Apple IIc Technical Reference 2nd Ed., the MIG has the following signals.

Pin(s) Signal 1) Description
1 IOSEL* “Tied to RESET*” (schematic verifies this)
2-7 A5-A11 System address bits 5-11
8 BUSEN* “Output that indicates valid access to MIG address space”
9 R/W System bus read/write control line
10 PH1 System clock
11 EN2X* “Input that indicates an access to address $C0nx is occurring, where n is $9-$E [sic]; an access to $C0nx addresses port n-8”
12 VSS
13 ROMEN1* “Input that indicates an accesses to lower ROM bank space $C100-$DFFF is occurring”
14 RESET* “System reset or ROM address 14”
15 IWMRES “Latched output bit to reset IWM”
16 INTEN* “Latched output bit to enable internal drive”
17 ENB2 “Follows EN2X* or ROMEN1* if addressing mapped device space to select external drives”
18 3.5DRIVE* “Latched output bit to select 5.25 in. or 3.5 in. drives”
19 HDSEL “Latched output bit used for 3.5 in. drives” (head select)“
20 ROMEN2* “ROM enable output line, follows ROMEN1*”
21 RAMEN* “RAM enable output line to 2 KB RAM buffer”
25 VDD
28-26,24-22 RAMA5-RAMA10 RAM buffer address bit 5-10

Analysis

Key points about the MIG based on the above and the schematic:

  1. It doesn't decode the lower 5 bits of the address bus. Thus the MIG address space must be broken down into 32-byte chunks.
  2. RAMA5-RAMA10 combined with the lower 5 bits of the address bus are used to address the 2K SRAM.
  3. It doesn't decode A12-A15, so on a 16-bit bus its address space must repeat every $1000 bytes without other selection logic. This logic is the ROMEN1* signal. This explains why the MIG appears at both $CE00 and $DE00.
  4. It doesn't have pins for the data bus at all. Therefore it cannot possibly directly provide state information. However it could provide it indirectly by selectively not enabling the RAM chip select during a read or write.
  5. Since the MIG appears at $xE00-$xFFF, the MIG considers itself selected when A11-A5 = 111xxxx, in this case it does not pass ROMEN1* to ROMEN2*. It cannot drive the data bus (no data lines) therefore it can only perform an action or assert RAMEN* to select the 2K SRAM.
  6. The MIG monitors I/O space accesses via EN2X*, presumably to watch the IWM. That being said, the MIG can't monitor that closely since it has no data lines, nor can it see which specific I/O addresses are being accessed due to missing A0-A4.

Other outstanding questions:

  • What does ENB2 do?

MIG Address Space

Obvious access to the MIG is via a 512-byte (or more… see below) window at $CE00 (mirrored at $DE00) that becomes visible only when the aux firmware bank is selected.

Address(s) Use
$CE00 - $CE1F MIG RAM window
$CE20 Increment RAM window page
$CE3D Firmware has one STA (at $CB86) and one LDA (at $CC29) here
$CE3E Firmware has one LDA (at $DC49) and one LDX (at $DC71) here
$CE3F Firmware has two LDX (at $DC9E and $DCC9) here
$CE40 Firmware addresses this in multiple locations via BIT, LDA, and STA
$CE60 - $CE7F Creates a 3 ms pulse (discovered via oscilloscope) on HDSEL. Firmware accesses $CE60 via BIT, LDA, and STA
$CE80 - $CE9F Creates a 1/2 ms pulse (discovered via oscilloscope) on ENB2, firmware does not appear to use
$CEA0 Set RAM window page 0 (maybe through $CEBF)
$CECD Firmware has one CMP (at $CCB8) here
$CEE0 - $CEFF Firmware does not address this range
$CF00 - $CFFF Firmware does not address this range

Notable item in firmware: There are STA $CCx0 where X = 4, 8, or C in several locations, always adjacent to a MIG or IWM access. What on earth does that do? Presumably the MIG also responds to these, so the MIG's address space may very well overlap with the ROM from $CC00 to $CDFF. If so, obviously only writes would affect the MIG in those locations.

MIG RAM

The visible 32-byte page of the RAM window is selected as follows:

  • Access $CEA0 - Set page 0
  • Access $CE20 - Increment page

The following page usages have been noted:

  • Page 0 and 1 - Used by the 3.5" firmware.
  • Page 2 - Used by the accelerator firmware.
  • Page 3+ - Used by the 3.5" firmware.

The contents of the MIG RAM can be viewed using my MIG Inspector.

MIG I/O

TBD.

1)
* = active low