Apple II I/O Page

Borrowed heavily from Jon Relay and updated.

Unless stated otherwise, all IIe I/O applies to the Apple IIe Card for Macintosh LC (“IIe PDS Card”).

Address List

Address Name Comp1) Act2) Description
C000 49152 KBD OECG R Last Key Pressed + 128
80STOREOFF ECG W Use $C002-$C005 for Aux Memory
C001 49153 80STOREON ECG W Use PAGE2 for Aux Memory
C002 49154 RDMAINRAM ECG W If 80STORE Off: Read Main Mem $0200-$BFFF
C003 49155 RDCARDRAM ECG W If 80STORE Off: Read Aux Mem $0200-$BFFF
C004 49156 WRMAINRAM ECG W If 80STORE Off: Write Main Mem $0200-$BFFF
C005 49157 WRCARDRAM ECG W If 80STORE Off: Write Aux Mem $0200-$BFFF
C006 49158 SETSLOTCXROM E G W Peripheral ROM ($C100-$CFFF)
C007 49159 SETINTCXROM E G W Internal ROM ($C100-$CFFF)
C008 49160 SETSTDZP ECG W Main Stack and Zero Page
C009 49161 SETALTZP ECG W Aux Stack and Zero Page
C00A 49162 SETINTC3ROM E G W ROM in Slot 3
C00B 49163 SETSLOTC3ROM E G W ROM in Aux Slot
C00C 49164 CLR80VID ECG W 40 Columns
C00D 49165 SET80VID ECG W 80 Columns
C00E 49166 CLRALTCHAR ECG W Primary Character Set
C00F 49167 SETALTCHAR ECG W Alternate Character Set
C010 49168 KBDSTRB OECG WR Keyboard Strobe
C011 49169 RDLCBNK2 ECG R7 Status of Selected $Dx Bank
C012 49170 RDLCRAM ECG R7 Status of $Dx ROM / $Dx RAM
C013 49171 RDRAMRD ECG R7 Status of Main/Aux RAM Reading
C014 49172 RDRAMWRT ECG R7 Status of Main/Aux RAM Writing
C015 49173 RDCXROM E G R7 Status of Periph/ROM Access
RSTXINT C R Reset Mouse X0 Interrupt
C016 49174 RDALTZP ECG R7 Status of Main/Aux Stack and Zero Page
C017 49175 RDC3ROM E G R7 Status of Slot 3/Aux Slot ROM
RSTYINT C R Reset Mouse Y0 Interrupt
C018 49176 RD80STORE ECG R7 Status of $C002-$C005/PAGE2 for Aux Mem
C019 49177 RDVBL E G R7 Vertical Blanking (E:1=drawing G:0=drawing)
RSTVBL C R Reset Vertical Blanking Interrupt
C01A 49178 RDTEXT ECG R7 Status of Text/Graphics
C01B 49179 RDMIXED ECG R7 Status of Full Screen/Mixed Graphics
C01C 49180 RDPAGE2 ECG R7 Status of Page 1/Page 2
C01D 49181 RDHIRES ECG R7 Status of LoRes/HiRes
C01E 49182 RDALTCHAR ECG R7 Status of Primary/Alternate Character Set
C01F 49183 RD80VID ECG R7 Status of 40/80 Columns
C020 49184 TAPEOUT OE R Toggle Cassette Tape Output (not on IIe PDS Card)
C021 49185 MONOCOLOR G W 7 Color/Mono
C022 49186 TBCOLOR G V Screen Color: Low Nibble is BG, High Nibble is Text
C023 49187 VGCINT G V Video Graphics Controller Interrupts:
b0-2=ext,scan,1sec enable b4-7=ext,scan,1sec,VGC
C024 49188 MOUSEDATA G V Mouse Data: High Bit is Button, Other Bits are Movement
C025 49189 KEYMODREG G V Modifier Keys:
Bit 7: Command, Bit 6: Option,
Bit 5: NotUsed, Bit 4: Keypad,
Bit 3: Repeat, Bit 2: Caps,
Bit 1: Control, Bit 0: Shift
C026 49190 DATAREG G V ADB Command/Data
b0-2=# b3=valid b4=clr buf b5=reboot b6=abort b7=status
C027 49191 KMSTATUS G V ADB Status
b0=cmdFull b1=mouseX b2=keyIntr b3=key
b4=cmdIntr b5=data 6=mouseInt 7=mouse
C028 49192 ROMBANK C W ROM bank select toggle
ROMBANK G WR ROM bank select toggle (ROM 0/1 IIgs only)
Switch $D000-FFFF between
$FFD000-$FFFFFF and $FF9000-$FFBFFFF
MAINROM M WR IIe PDS Card: Select main firmware
C029 49193 NEWVIDEO G V New Video: 129=SHR, 1=None, Bit 6=Linearize, Bit 5=BW
AUXROM M WR IIe PDS Card: Select aux firmware
C02B 49195 LANGSEL G Bit 3=Secondary Bit 4=50Hz Bits 5-7=Display Language
??? M V IIe PDS Card: Control register
C02C 49196 CHARROM G Addr for test mode read of character ROM
C02D 49197 SLTROMSEL G Slot Register; Bits 1-7=use slot card
C02E 49198 VERTCNT G Addr for read of video cntr bits V5-VB
Vertical addr / 2)
C02F 49199 HORIZCNT G Addr for read of video cntr bits VA-H0
Vertical low bit, Horizontal
C030 48200 SPKR OECG R Toggle Speaker
C031 49201 DISKREG G Disk Interface: Bit 6=3.5 enable, Bit 7=head select 1
C032 49202 SCANINT G V VGC Interrupt-Clear
C033 49203 CLOCKDATA G Clock data register
C034 49204 CLOCKCTL G Clock control register
b7=dclk, b6=read(1)/write, b5=chip enable after xfer
b0-3=borderColor b5=stopBit b6=read b7=start
C035 49205 SHADOW G Inhibit Shadowing:
Bit 6: I/O Memory, Bit 5: Alternate Display Mode
Bit 4: Auxilary HGR, Bit 3: Super HiRes, Bit 2: HiRes Page 2
Bit 1: HiRes Page 1, Bit 0: Text/LoRes
C036 49206 CYAREG G Bits 0-3=Disk Detect slots 4-7 Bit 4=Shadow All Banks Bit 7=Fast
C037 49207 DMAREG G DMA Bank register
C038 49208 SCCBREG G SCC Command Channel B
C039 49209 SCCAREG G SCC Command Channel A
C03A 49210 SCCBDATA G SCC Data Channel B
C03B 49211 SCCADATA G SCC Data Channel A
C03C 49212 SOUNDCTL G V Sound Settings:
Bits 0-3=Volume Bit 5=AutoIncr
Bit 6=RAM Bit 7=Busy
C03D 49213 SOUNDDATA G Sound Data
C03E 49214 SOUNDADRL G Address Pointer L
C03F 49215 SOUNDADRH G Address Pointer H
C040 49216 STROBE OE R Game I/O Strobe Output
RDXYMSK C R7 Read X0/Y0 Interrupt
C041 49217 RDVBLMSK C R7 Read VBL Interrupt
INTEN G WR Mega II interrupt enable
b4 = 1/4s, b3 = VBL,
b2-b1 = mouse sw & move,
b0 = enable Mega II mouse
C042 49218 RDX0EDGE C R7 Read X0 Edge Selector
C043 49219 RDY0EDGE C R7 Read Y0 Edge Selector
C044 49220 MMDELTAX G V Mega II Mouse Delta Movement X
C045 49221 MMDELTAY G V Mega II Mouse Delta Movement Y
C046 49222 DIAGTYPE G W7 Bit 7 1 = Burn in diags, 0 = burn-in diag
INTFLAG G R Mega II flags:
b0=IRQ b1=MMmov b2=MMbut b3=VBL b4=qsec
b5=AN3 b6=mouse was down b7=mouse is down
C047 49223 CLRVBLINT G Clear Mega II VBL Interrupt
C048 49224 CLRXYINT G Clear Mega II MM Interrupt
C048 49224 RSTXY C WR Reset X and Y Interrupts
C04F 49231 EMUBYTE WR Emulation ID byte:
write once, then read once for program being used, read again for version number.
$FE=Bernie, $16=Sweet16, $47 = GSport, $4B=KEGS, $AB=Appleblossom
C050 49232 TXTCLR OECG WR Display Graphics
C051 49233 TXTSET OECG WR Display Text
C052 49234 MIXCLR OECG WR Display Full Screen
C053 49235 MIXSET OECG WR Display Split Screen
C054 49236 TXTPAGE1 OECG WR Display Page 1
C055 49237 TXTPAGE2 OECG WR If 80STORE Off: Display Page 2
ECG WR If 80STORE On: Read/Write Aux Display Mem
C056 49238 LORES OECG WR Display LoRes Graphics
C057 49239 HIRES OECG WR Display HiRes Graphics
C058 49240 CLRAN0 OE G WR If IOUDIS off: Annunciator 0 Off
DISXY C WR If IOUDIS on: Mask X0/Y0 Move Interrupts
ZIPGS_58 G W Write to force power on/reset to COLD
C059 49241 SETAN0 OE G WR If IOUDIS off: Annunciator 0 On
ENBXY C WR If IOUDIS on: Allow X0/Y0 Move Interrupts
ZIPGS_59 G WR ZipGS control register
C05A 49242 CLRAN1 OE G WR If IOUDIS off: Annunciator 1 Off
DISVBL C WR If IOUDIS on: Disable VBL Interrupts
CGGA_5A P W IIc+/Zip Chip: Write $A5 to lock registers
Write $5A * 4 to unlock registers
Write anything else to slow to standard system clock speed
C05A ZIPGS_5A G RW ZipGS: W: same as above
R: b7-b4: clock divider
C05B 49243 SETAN1 OE G WR If IOUDIS off: Annunciator 1 On
ENVBL C WR If IOUDIS on: Enable VBL Interrupts
CGGA_5B P WR IIc+/Zip Chip: Write: enable accelerator, Read: status
ZIPGS_5B G WR ZipGS: W: enable card, R: status
C05C 49244 CLRAN2 OE G WR If IOUDIS off: Annunciator 2 Off
X0EDGE C WR If IOUDIS on: Interrupt on X0 Rising
CGGA_5C P WR IIc+/Zip Chip: Slot speed & Speaker Delay
ZIPGS_5C G WR ZipGS: Same as Zip/CGGA
??? M R IIe PDS Card: b4 = speed selected in option panel (1 = fast)
C05D 49245 SETAN2 OE G WR If IOUDIS off: Annunciator 2 On
X0EDGE C WR If IOUDIS on: Interrupt on X0 Falling
CGGA_5D P W IIc+/Zip Chip: Clock divider
ZIPGS_5D G W ZipGS: b7-b4 = Clock divider
C05E 49246 CLRAN3 OE G WR If IOUDIS off: Annunciator 3 Off
Y0EDGE C WR If IOUDIS on: Interrupt on Y0 Rising
DHIRESON ECG WR In 80-Column Mode: Double Width Graphics
CGGA_5E P WR IIc+/Zip Chip: Write: b7 = disable I/O delay, Read: soft switch state
ZIPGS_5E G R ZipGS: Read last tag and force next write to create trash tag value
C05F 49247 SETAN3 OE G WR If IOUDIS off: Annunciator 3 On
Y0EDGE C WR If IOUDIS on: Interrupt on Y0 Falling
DHIRESOFF ECG WR In 80-Column Mode: Single Width Graphics
CGGA_5F P WR IIc+/Zip Chip: Paddle delay & Language Card cache
ZIPGS_5F G R ZipGS: Read last tag and reset cshupd
C060 49248 TAPEIN OE R7 Read Cassette Input (not on IIe PDS Card)
C R7 Status of 80/40 Column Switch (not IIc Plus)
BUTN3 G R7 Switch Input 3
C061 49249 BUTN0 OECG R7 Switch Input 0
Open Apple/Command (not II/II+)
C062 49250 BUTN1 OECG R7 Switch Input 1
Solid Apple/Option (not II/II+)
C063 49251 BUTN2 OE G R7 Switch Input 2
Shift Key (if shift key mod in place)
C R7 Bit 7 = Mouse Button Not Pressed
C064 49252 PADDL0 OECG R7 Analog Input 0
C065 49253 PADDL1 OECG R7 Analog Input 1
C066 49254 PADDL2 OE G R7 Analog Input 2
RDMOUX1 C R7 Mouse Horiz Position
C067 49255 PADDL3 OE G R7 Analog Input 3
RDMOUY1 C R7 Mouse Vert Position
C068 49256 STATEREG G V b0=INTCXROM b1=ROMBANK b2=LCBNK2 b3=RDROM
b4=RAMWRT b5=RAMRD b6=PAGE2 b7=ALTZP
C06A 49258 FASTCHIP_6A E W FastChip //e: Lock/Unlock register
C06B 49259 FASTCHIP_6B E W FastChip //e: Enable other registers
E R7 FastChip //e: b7=1 Registers enabled
C06C 49260 FASTCHIP_6C E V FastChip //e: Slot speed register
C06D 49261 TESTREG ???? Test Mode Bit Register
FASTCHIP_6D E V FastChip //e: Clock speed register
C06E 49262 CLRTM ???? Clear Test Mode
FASTCHIP_6E E V FastChip //e: Config register select
C06F 49263 ENTM ???? Enable Test Mode
FASTCHIP_6F E V FastChip //e: Config register value
C070 49264 PTRIG OECG R Analog Input Reset
C WR Analog Input Reset + Reset VBLINT Flag
C071–C07F G 15 bytes of code for IRQ/BRK handling
C072 49266 ??? M W IIe PDS Card: unknown
C073 49267 BANKSEL EC W RAMworks-style Aux RAM Card bank select
C074 49268 TRANSWARP OE W Transwarp speed: 0 = max speed, 1 = 1 MHz, 3 = disable
C077 49271 BLOSSOM W Appleblossom Special I/O Address
$C1=Install clock driver
$CC=Get time in input buffer
$CF=get time in ProDOS global page
C078 49272 C W Disable IOU Access
C079 49273 C W Enable IOU Access
C07E 49278 IOUDISON EC W Disable IOU (not on IIe PDS Card)
RDIOUDIS EC R7 Status of IOU Disabling (not on IIe PDS Card)
C07F 49279 IOUDISOFF EC W Enable IOU (not on IIe PDS Card)
RDDHIRES EC R7 Status of Double HiRes
C090–C09F O slot 0
C080 49280 OECG R Read RAM bank 2; no write
C081 49281 ROMIN OECG RR Read ROM; write RAM bank 2
C082 49282 OECG R Read ROM; no write
C083 49283 LCBANK2 OECG RR Read/write RAM bank 2
C084–C087 R Saturn RAM Card: Select banks 0-3
C084 49284 OECG R Read RAM bank 2; no write
C085 49285 ROMIN OECG RR Read ROM; write RAM bank 2
C086 49286 OECG R Read ROM; no write
C087 49287 LCBANK2 OECG RR Read/write RAM bank 2
C088 49288 OECG R Read RAM bank 1; no write
C089 49289 OECG RR Read ROM; write RAM bank 1
C08A 49290 OECG R Read ROM; no write
C08B 49291 OECG RR Read/write RAM bank 1
C08C–C08F R Saturn RAM Card: Select banks 4-7
C08C 49292 OECG R Read RAM bank 1; no write
C08D 49293 OECG RR Read ROM; write RAM bank 1
C08E 49294 OECG R Read ROM; no write
C08F 49295 OECG RR Read/write RAM bank 1
C090–C09F OE G slot 1 (not IIe PDS Card)
C098 C V ACIA 1 tx/rx data register
C099 C V ACIA 1 tx/rx status register
C09A C V ACIA 1 tx/rx command register
C09B C V ACIA 1 tx/rx control register
C0A0–C0AF OE G slot 2 (not IIe PDS Card)
C098 C V ACIA 2 tx/rx data register
C099 C V ACIA 2 tx/rx status register
C09A C V ACIA 2 tx/rx command register
C09B C V ACIA 2 tx/rx control register
C0B0–C0BF OE G slot 3 (not IIe PDS Card)
C0C0–C0CF OE G slot 4 (not IIe PDS Card)
C0C0 ADDRL C V IIc Mem Expansion: Address low byte
C0C1 ADDRM C V IIc Mem Expansion: Address middle byte
C0C2 ADDRH C V IIc Mem Expansion: Address high byte
C0C3 DATA C V IIc Mem Expansion: Address data byte
C0D0–C0DF OE G slot 5 (not IIe PDS Card)
C0E0–C0EF OE G slot 6 (not IIe PDS Card)
C0E0 MCG IWM:PH0 off
C0E1 MCG IWM:PH0 on
C0E2 MCG IWM:PH1 off
C0E3 MCG IWM:PH1 on
C0E4 MCG IWM:PH2 off
C0E5 MCG IWM:PH2 on
C0E6 MCG IWM:PH3 off
C0E7 MCG IWM:PH3 on
C0E8 MCG IWM:motor off
C0E9 MCG IWM:motor on
C0EA MCG IWM:sel drive 1
C0EB MCG IWM:sel drive 2
C0EC MCG IWM:Q6 off (read)
C0ED MCG IWM:Q6 on (WP sense)
C0EE MCG IWM:Q7 off (WP sense/read)
C0EF MCG IWM:Q7 on (Write)
C0F0–C0FF OE G slot 7 (not IIe PDS Card)

IIgs Quick Ref Table

Borrowed from here.

C02x C03x C04x C05x C06x
0 rsvd Speaker rsvd Graphics Switch 3
1 MONO 3.5 Disk Mouse Int Text Switch 1
2 TXT Color Scan Int rsvd Unmixed Switch 1
3 VGC Int Clock Data rsvd Mixed Switch 2
4 MouseData Clock Ctrl M Delta X Text 1 Paddle 0
5 Key Mods Shadow M Delta Y Text 2 Paddle 1
6 KM Data Speed M Flags Lo Res Paddle 2
7 KM Status DMA Bank VBL Int Hi Res Paddle 3
8 ROM Bank SCC B Cmd XY Int Clr AN0 State Reg
9 New Video SCC A Cmd rsvd Set AN0 rsvd
A rsvd SCC B Data rsvd Clr AN1 rsvd
B Lang Sel SCC A Data rsvd Set AN1 rsvd
C CharROM Sound Ctrl rsvd Clr AN2 rsvd
D Slot ROM Sound Data rsvd Set AN2 Test Mode
E Vert Cnt Sound AdrL rsvd Clr AN3 Test Off
F Horiz Cnt Sound AdrH rsvd Set AN3 Test On
1)
O = Apple II+, E = Apple IIe, C = Apple IIc and IIc Plus, P = Apple IIc Plus Only, G = Apple IIgs, M = IIe PDS Card Only
2)
R = Read, W = Write, 7 = Bit 7, V = register