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Apple IIc Plus Accelerator

The Apple IIc Plus accelerator is essentially a Zip Chip broken out into its discrete components, as Apple licensed the technology from Zip Technologies. All of the registers function exactly like a 4 MHz Zip Chip.


The firmware for maintaining the accelerator is in the aux bank of the firmware, at $FD00. My disassembly and analysis can be found here. The firmware as shipped by Apple contains numerous bugs, as annotated in the disassembly. Replacement firmware can be found as part of ROM 5X.


The stock firmware uses MIG RAM page 2 as follows:

  • $00 - powerup byte 1 - $33 after init.
  • $01 - powerup byte 2 - $55 after init.
  • $02,$03 - current accelerator control word.
  • $04 - keyboard keypress at RESET time, used to detect ESC during reset.
  • $05-$08 - copies of what should be in Zip Chip $c05c-$c05f registers (respectively).
  • $10-$17 - used to save zero page locations $00-$07.
  • Others - apparently unused.

Zero Page Use

When the accelerator firmware is called, either via reset or through the documented mechanism, it saves $00-$07 to the MIG RAM and then uses the locations. When the code exits it is supposed to restore the locations, but due to a bug $00 is not restored properly.

  • $00 - temporary value
  • $01 - stack pointer at call time
  • $02 - command number
  • $03-$04 - user buffer pointer
  • $05 - exit code
  • $06-$07 - unused