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mg_notes:cpm:softcard_cpm_ref [2018/07/03 11:30]
M.G. [Softcard CP/M Reference]
mg_notes:cpm:softcard_cpm_ref [2019/09/30 18:04]
M.G. [The Apple CP/M Disk Parameter Tables]
Line 73: Line 73:
 Turn on your Apple II. Turn on your Apple II.
  
 +==== DIP Switches ====
  
 +The four DIP switches are normally OFF for CP/M operation. ​ Their functions are:
 +
 +^ Switch ^ Function when ON ^
 +| 1-1    | Disable address translation. |
 +| 1-2    | Higher priority DMA devices cause SoftCard to relinguish bus. |
 +| 1-3    | Pass NMI line to Z80. |
 +| 1-4    | Pass IRQ line to Z80. |
 ===== Apple Softcard CP/M specific programs ===== ===== Apple Softcard CP/M specific programs =====
  
Line 182: Line 190:
  
 ^ Key ^ Action ^ ^ Key ^ Action ^
-| <​key>​Ctrl-S</​key>​ | Temporarily stops character output to TTY:  Output is resumed when any character is typed |+| <​key>​Ctrl-'S'</​key>​ | Temporarily stops character output to TTY:  Output is resumed when any character is typed |
 | <​key>​Ctrl-P</​key>​ | Sends all character output to LPT: as well as to TTY: \\ This "​printer echo" mode remains in effect until another <​key>​Ctrl-P</​key>​ is typed. | | <​key>​Ctrl-P</​key>​ | Sends all character output to LPT: as well as to TTY: \\ This "​printer echo" mode remains in effect until another <​key>​Ctrl-P</​key>​ is typed. |
  
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 Because of the way the 6502 is "put to sleep" by the Z-80 SoftCard using the Because of the way the 6502 is "put to sleep" by the Z-80 SoftCard using the
 DMA line on the Apple bus, ALL interrupt processing must be handled by the DMA line on the Apple bus, ALL interrupt processing must be handled by the
-6502.  ​AN interrupt can occur at two times: while in Z-80 mode and while in+6502.  ​An interrupt can occur at two times: while in Z-80 mode and while in
 6502 mode: 6502 mode:
  
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 ===== Microsoft SoftCard Version 2.23 BIOS ===== ===== Microsoft SoftCard Version 2.23 BIOS =====
  
-THe Microsoft 2.20B BIOS uses some ingainly ​fixes to correct a few+THe Microsoft 2.20B BIOS uses some ungainly ​fixes to correct a few
 problems, but still a few problems remain in the area of hardware problems, but still a few problems remain in the area of hardware
 interfacing. ​ Most of these problems are corrected in the SoftCard interfacing. ​ Most of these problems are corrected in the SoftCard
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 The hardware interfacing is greatly improved because version 2.23 The hardware interfacing is greatly improved because version 2.23
 uses Apple Computer'​s protocols for operating what Apple calls uses Apple Computer'​s protocols for operating what Apple calls
-Formware ​Cards. ​ Most of the cards that can operate a host of+Firmware ​Cards. ​ Most of the cards that can operate a host of
 peripheral devices and have them do all sorts of neat tricks are peripheral devices and have them do all sorts of neat tricks are
 Firmware Cards. ​ Version 2.20B could not identify Firmware Cards and Firmware Cards. ​ Version 2.20B could not identify Firmware Cards and
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 | $DD0 | $DE0   | Firmware Card initialization routine, followed by a routine that uses the Apple protocol for firmware I/O | | $DD0 | $DE0   | Firmware Card initialization routine, followed by a routine that uses the Apple protocol for firmware I/O |
 | $DE1 | $DEE   | Firmware Card output routine | | $DE1 | $DEE   | Firmware Card output routine |
-| $DEF | $DFA   ​| ​Formware ​Card routine which waits for card to accept I/O |+| $DEF | $DFA   ​| ​Firmware ​Card routine which waits for card to accept I/O |
 | $E00 | $E02   | CP/M entry to the warm loader routine | | $E00 | $E02   | CP/M entry to the warm loader routine |
 | $E03 | $E08   | Entry to CP/M RWTS routine on Language Card bank 1 | | $E03 | $E08   | Entry to CP/M RWTS routine on Language Card bank 1 |
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 ^ Physical format: ​ ^  A  ^  B  ^  C  ^  D  ^ ^ Physical format: ​ ^  A  ^  B  ^  C  ^  D  ^
-^                  ^  Apple CP/M  ^^  Enhanced ​ ^  Standard ​ ^ +^                  ^  Apple CP/M  ^^  Enhanced ​CP/M  ​^ ​ Standard ​\\ CP/M  ^ 
-^                  ^  13-sect ​ ^  16-sect ​ ^  80-trk/16-sec/2-side ​ ^  8" SSSD  ^+^                  ^  13-sect ​ ^  16-sect ​ ^  80-trk ​\\ 16-sec ​\\ 2-side ​ ^  8" SSSD  ^
 | Bytes/​sector ​    ​| ​   256 |       256 |             256 |             128 | | Bytes/​sector ​    ​| ​   256 |       256 |             256 |             128 |
 | Sectors/​track ​   |     13 |        16 |              16 |              26 | | Sectors/​track ​   |     13 |        16 |              16 |              26 |
Line 1433: Line 1441:
 **Apple CP/M DPB - Disk Parameter Block** **Apple CP/M DPB - Disk Parameter Block**
  
-^             ​^ ​      ​A ^     ​B ^     ​C ^     ​D ^ ^+^             ​^ ​        ​  ​  ​  ​  ​  ^ ^ 
 +^ ^ Apple CP/M    ^^  Enhanced \\ CP/M  ^  Standard \\ CP/​M  ​^ ^
 | SPT 16b     ​| ​     26 |    32 |    32 |    26 | 128-byte Logical Sectors/​Track | | SPT 16b     ​| ​     26 |    32 |    32 |    26 | 128-byte Logical Sectors/​Track |
 | BSH  8b     ​| ​      3 |     3 |     4 |     3 | Block shift factor | | BSH  8b     ​| ​      3 |     3 |     4 |     3 | Block shift factor |