Differences
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mg_notes:general:io_page [2017/10/12 13:09] M.G. cleanup/clarification |
mg_notes:general:io_page [2022/08/01 18:37] (current) M.G. [Address List] clarify KBD |
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| Borrowed heavily from [[http://www.kreativekorp.com/miscpages/a2info/iomemory.shtml|Jon Relay]] and updated. | Borrowed heavily from [[http://www.kreativekorp.com/miscpages/a2info/iomemory.shtml|Jon Relay]] and updated. | ||
| + | |||
| + | Unless stated otherwise, all IIe I/O applies to the Apple IIe Card for Macintosh LC ("IIe PDS Card"). | ||
| + | |||
| + | ===== Address List ===== | ||
| ^ Address ^ Name ^ Comp((O = Apple II+, E = Apple IIe, C = Apple IIc and IIc Plus, P = Apple IIc Plus Only, G = Apple IIgs, M = IIe PDS Card Only)) ^ Act((R = Read, W = Write, 7 = Bit 7, V = register)) ^ Description ^ | ^ Address ^ Name ^ Comp((O = Apple II+, E = Apple IIe, C = Apple IIc and IIc Plus, P = Apple IIc Plus Only, G = Apple IIgs, M = IIe PDS Card Only)) ^ Act((R = Read, W = Write, 7 = Bit 7, V = register)) ^ Description ^ | ||
| - | | C000 49152 | KBD | OECG | R | Last Key Pressed + 128 | | + | | C000 49152 | KBD | OECG | R | Last Key Pressed (+ 128 if strobe not cleared) | |
| | | 80STOREOFF | ECG | W | Use $C002-$C005 for Aux Memory | | | | 80STOREOFF | ECG | W | Use $C002-$C005 for Aux Memory | | ||
| | C001 49153 | 80STOREON | ECG | W | Use PAGE2 for Aux Memory | | | C001 49153 | 80STOREON | ECG | W | Use PAGE2 for Aux Memory | | ||
| Line 15: | Line 19: | ||
| | C008 49160 | SETSTDZP | ECG | W | Main Stack and Zero Page | | | C008 49160 | SETSTDZP | ECG | W | Main Stack and Zero Page | | ||
| | C009 49161 | SETALTZP | ECG | W | Aux Stack and Zero Page | | | C009 49161 | SETALTZP | ECG | W | Aux Stack and Zero Page | | ||
| - | | C00A 49162 | SETINTC3ROM | E G | W | ROM in Slot 3 | | + | | C00A 49162 | SETINTC3ROM | E G | W | Use Internal Slot 3 ROM | |
| - | | C00B 49163 | SETSLOTC3ROM | E G | W | ROM in Aux Slot | | + | | C00B 49163 | SETSLOTC3ROM | E G | W | Use Card Slot 3 ROM | |
| | C00C 49164 | CLR80VID | ECG | W | 40 Columns | | | C00C 49164 | CLR80VID | ECG | W | 40 Columns | | ||
| | C00D 49165 | SET80VID | ECG | W | 80 Columns | | | C00D 49165 | SET80VID | ECG | W | 80 Columns | | ||
| Line 48: | Line 52: | ||
| | C026 49190 | DATAREG | G | V | ADB Command/Data \\ b0-2=# b3=valid b4=clr buf b5=reboot b6=abort b7=status | | | C026 49190 | DATAREG | G | V | ADB Command/Data \\ b0-2=# b3=valid b4=clr buf b5=reboot b6=abort b7=status | | ||
| | C027 49191 | KMSTATUS | G | V | ADB Status \\ b0=cmdFull b1=mouseX b2=keyIntr b3=key \\ b4=cmdIntr b5=data 6=mouseInt 7=mouse | | | C027 49191 | KMSTATUS | G | V | ADB Status \\ b0=cmdFull b1=mouseX b2=keyIntr b3=key \\ b4=cmdIntr b5=data 6=mouseInt 7=mouse | | ||
| - | | C028 49192 | ROMBANK | CG | W | ROM bank select toggle (IIgs = ROM 0/1 only) | | + | | C028 49192 | ROMBANK | C | W | ROM bank select toggle. \\ Not on unmodified machines with original 16K ROM. | |
| + | | | ROMBANK | G | WR | ROM bank select toggle (ROM 0/1 IIgs only) \\ Switch $D000-FFFF between \\ $FFD000-$FFFFFF and $FF9000-$FFBFFFF | | ||
| | | MAINROM | M | WR | IIe PDS Card: Select main firmware | | | | MAINROM | M | WR | IIe PDS Card: Select main firmware | | ||
| | C029 49193 | NEWVIDEO | G | V | New Video: 129=SHR, 1=None, Bit 6=Linearize, Bit 5=BW | | | C029 49193 | NEWVIDEO | G | V | New Video: 129=SHR, 1=None, Bit 6=Linearize, Bit 5=BW | | ||
| Line 56: | Line 61: | ||
| | C02C 49196 | CHARROM | G | | Addr for test mode read of character ROM | | | C02C 49196 | CHARROM | G | | Addr for test mode read of character ROM | | ||
| | C02D 49197 | SLTROMSEL | G | | Slot Register; Bits 1-7=use slot card | | | C02D 49197 | SLTROMSEL | G | | Slot Register; Bits 1-7=use slot card | | ||
| - | | C02E 49198 | VERTCNT | G | | Addr for read of video cntr bits V5-VB | | + | | C02E 49198 | VERTCNT | G | | Addr for read of video cntr bits V5-VB \\ Vertical addr / 2) | |
| - | | C02F 49199 | HORIZCNT | G | | Addr for read of video cntr bits VA-H0 | | + | | C02F 49199 | HORIZCNT | G | | Addr for read of video cntr bits VA-H0 \\ Vertical low bit, Horizontal | |
| | C030 48200 | SPKR | OECG | R | Toggle Speaker | | | C030 48200 | SPKR | OECG | R | Toggle Speaker | | ||
| - | | C031 49201 | DISKREG | G | | Disk Interface: Bit 6=3.5 Bit 7=RWHead 1 | | + | | C031 49201 | DISKREG | G | | Disk Interface: Bit 6=3.5 enable, Bit 7=head select 1 | |
| | C032 49202 | SCANINT | G | V | VGC Interrupt-Clear | | | C032 49202 | SCANINT | G | V | VGC Interrupt-Clear | | ||
| - | | C033 49203 | CLOCKDATA | G | | Interface to Battery RAM (undocumented) | | + | | C033 49203 | CLOCKDATA | G | | Clock data register | |
| - | | C034 49204 | CLOCKCTL | G | | b0-3=borderColor b5=stopBit b6=read b7=start | | + | | C034 49204 | CLOCKCTL | G | | Clock control register \\ b7=dclk, b6=read(1)/write, b5=chip enable after xfer \\ b0-3=borderColor b5=stopBit b6=read b7=start | |
| | C035 49205 | SHADOW | G | | Inhibit Shadowing: \\ Bit 6: I/O Memory, Bit 5: Alternate Display Mode \\ Bit 4: Auxilary HGR, Bit 3: Super HiRes, Bit 2: HiRes Page 2 \\ Bit 1: HiRes Page 1, Bit 0: Text/LoRes | | | C035 49205 | SHADOW | G | | Inhibit Shadowing: \\ Bit 6: I/O Memory, Bit 5: Alternate Display Mode \\ Bit 4: Auxilary HGR, Bit 3: Super HiRes, Bit 2: HiRes Page 2 \\ Bit 1: HiRes Page 1, Bit 0: Text/LoRes | | ||
| - | | C036 49206 | CYAREG | G | | Bits 0-3=Disk Detect Bit 4=Shadow All Banks Bit 7=Fast | | + | | C036 49206 | CYAREG | G | | Bits 0-3=Disk Detect slots 4-7 Bit 4=Shadow All Banks Bit 7=Fast | |
| - | | C037 49207 | BMAREG | G | | Bit 5=BW | | + | | C037 49207 | DMAREG | G | | DMA Bank register | |
| | C038 49208 | SCCBREG | G | | SCC Command Channel B | | | C038 49208 | SCCBREG | G | | SCC Command Channel B | | ||
| | C039 49209 | SCCAREG | G | | SCC Command Channel A | | | C039 49209 | SCCAREG | G | | SCC Command Channel A | | ||
| Line 77: | Line 82: | ||
| | | RDXYMSK | C | R7 | Read X0/Y0 Interrupt | | | | RDXYMSK | C | R7 | Read X0/Y0 Interrupt | | ||
| | C041 49217 | RDVBLMSK | C | R7 | Read VBL Interrupt | | | C041 49217 | RDVBLMSK | C | R7 | Read VBL Interrupt | | ||
| - | | | INTEN | G | WR | | | + | | | INTEN | G | WR | Mega II interrupt enable \\ b4 = 1/4s, b3 = VBL, \\ b2-b1 = mouse sw & move, \\ b0 = enable Mega II mouse | |
| | C042 49218 | RDX0EDGE | C | R7 | Read X0 Edge Selector | | | C042 49218 | RDX0EDGE | C | R7 | Read X0 Edge Selector | | ||
| | C043 49219 | RDY0EDGE | C | R7 | Read Y0 Edge Selector | | | C043 49219 | RDY0EDGE | C | R7 | Read Y0 Edge Selector | | ||
| | C044 49220 | MMDELTAX | G | V | Mega II Mouse Delta Movement X | | | C044 49220 | MMDELTAX | G | V | Mega II Mouse Delta Movement X | | ||
| | C045 49221 | MMDELTAY | G | V | Mega II Mouse Delta Movement Y | | | C045 49221 | MMDELTAY | G | V | Mega II Mouse Delta Movement Y | | ||
| - | | C046 49222 | DIAGTYPE | ???? | | Self or Burn-In diagdistics: Bit 7=burn-in diag | | + | | C046 49222 | DIAGTYPE | G | W7 | Bit 7 1 = Burn in diags, 0 = burn-in diag | |
| - | | | INTFLAG | ???? | | b0=IRQ b1=MMmov b2=MMbut b3=VBL b4=qsec \\ b5=AN3 b6=mouse was down b7=mouse is down | | + | | | INTFLAG | G | R | Mega II flags: \\ b0=IRQ b1=MMmov b2=MMbut b3=VBL b4=qsec \\ b5=AN3 b6=mouse was down b7=mouse is down | |
| - | | C047 49223 | CLRVBLINT | ???? | | Clear VBL Interrupt | | + | | C047 49223 | CLRVBLINT | G | | Clear Mega II VBL Interrupt | |
| - | | C048 49224 | CLRXYINT | ???? | | Clear MM Interrupt | | + | | C048 49224 | CLRXYINT | G | | Clear Mega II MM Interrupt | |
| | C048 49224 | RSTXY | C | WR | Reset X and Y Interrupts | | | C048 49224 | RSTXY | C | WR | Reset X and Y Interrupts | | ||
| | C04F 49231 | EMUBYTE | | WR | Emulation ID byte: \\ write once, then read once for program being used, read again for version number. \\ $FE=Bernie, $16=Sweet16, $47 = GSport, $4B=KEGS, $AB=Appleblossom | | | C04F 49231 | EMUBYTE | | WR | Emulation ID byte: \\ write once, then read once for program being used, read again for version number. \\ $FE=Bernie, $16=Sweet16, $47 = GSport, $4B=KEGS, $AB=Appleblossom | | ||
| Line 99: | Line 104: | ||
| | C058 49240 | CLRAN0 | OE G | WR | If IOUDIS off: Annunciator 0 Off | | | C058 49240 | CLRAN0 | OE G | WR | If IOUDIS off: Annunciator 0 Off | | ||
| | | DISXY | C | WR | If IOUDIS on: Mask X0/Y0 Move Interrupts | | | | DISXY | C | WR | If IOUDIS on: Mask X0/Y0 Move Interrupts | | ||
| + | | | ZIPGS_58 | G | W | Write to force power on/reset to COLD | | ||
| | C059 49241 | SETAN0 | OE G | WR | If IOUDIS off: Annunciator 0 On | | | C059 49241 | SETAN0 | OE G | WR | If IOUDIS off: Annunciator 0 On | | ||
| | | ENBXY | C | WR | If IOUDIS on: Allow X0/Y0 Move Interrupts | | | | ENBXY | C | WR | If IOUDIS on: Allow X0/Y0 Move Interrupts | | ||
| + | | | ZIPGS_59 | G | WR | ZipGS control register | | ||
| | C05A 49242 | CLRAN1 | OE G | WR | If IOUDIS off: Annunciator 1 Off | | | C05A 49242 | CLRAN1 | OE G | WR | If IOUDIS off: Annunciator 1 Off | | ||
| | | DISVBL | C | WR | If IOUDIS on: Disable VBL Interrupts | | | | DISVBL | C | WR | If IOUDIS on: Disable VBL Interrupts | | ||
| - | | | CGGA_5A | P | W | IIc+/Zip Chip: Write $A5 to lock registers \\ Write $5A * 4 to unlock registers \\ Write anything else to slow to 1 MHz | | + | | | CGGA_5A | P | W | IIc+/Zip Chip: Write $A5 to lock registers \\ Write $5A * 4 to unlock registers \\ Write anything else to slow to standard system clock speed | |
| + | | C05A | ZIPGS_5A | G | RW | ZipGS: W: same as above \\ R: b7-b4: clock divider | | ||
| | C05B 49243 | SETAN1 | OE G | WR | If IOUDIS off: Annunciator 1 On | | | C05B 49243 | SETAN1 | OE G | WR | If IOUDIS off: Annunciator 1 On | | ||
| | | ENVBL | C | WR | If IOUDIS on: Enable VBL Interrupts | | | | ENVBL | C | WR | If IOUDIS on: Enable VBL Interrupts | | ||
| | | CGGA_5B | P | WR | IIc+/Zip Chip: Write: enable accelerator, Read: status | | | | CGGA_5B | P | WR | IIc+/Zip Chip: Write: enable accelerator, Read: status | | ||
| + | | | ZIPGS_5B | G | WR | ZipGS: W: enable card, R: status | | ||
| | C05C 49244 | CLRAN2 | OE G | WR | If IOUDIS off: Annunciator 2 Off | | | C05C 49244 | CLRAN2 | OE G | WR | If IOUDIS off: Annunciator 2 Off | | ||
| | | X0EDGE | C | WR | If IOUDIS on: Interrupt on X0 Rising | | | | X0EDGE | C | WR | If IOUDIS on: Interrupt on X0 Rising | | ||
| | | CGGA_5C | P | WR | IIc+/Zip Chip: Slot speed & Speaker Delay | | | | CGGA_5C | P | WR | IIc+/Zip Chip: Slot speed & Speaker Delay | | ||
| + | | | ZIPGS_5C | G | WR | ZipGS: Same as Zip/CGGA | | ||
| | | ??? | M | R | IIe PDS Card: b4 = speed selected in option panel (1 = fast) | | | | ??? | M | R | IIe PDS Card: b4 = speed selected in option panel (1 = fast) | | ||
| | C05D 49245 | SETAN2 | OE G | WR | If IOUDIS off: Annunciator 2 On | | | C05D 49245 | SETAN2 | OE G | WR | If IOUDIS off: Annunciator 2 On | | ||
| | | X0EDGE | C | WR | If IOUDIS on: Interrupt on X0 Falling | | | | X0EDGE | C | WR | If IOUDIS on: Interrupt on X0 Falling | | ||
| | | CGGA_5D | P | W | IIc+/Zip Chip: Clock divider | | | | CGGA_5D | P | W | IIc+/Zip Chip: Clock divider | | ||
| + | | | ZIPGS_5D | G | W | ZipGS: b7-b4 = Clock divider | | ||
| | C05E 49246 | CLRAN3 | OE G | WR | If IOUDIS off: Annunciator 3 Off | | | C05E 49246 | CLRAN3 | OE G | WR | If IOUDIS off: Annunciator 3 Off | | ||
| | | Y0EDGE | C | WR | If IOUDIS on: Interrupt on Y0 Rising | | | | Y0EDGE | C | WR | If IOUDIS on: Interrupt on Y0 Rising | | ||
| | | DHIRESON | ECG | WR | In 80-Column Mode: Double Width Graphics | | | | DHIRESON | ECG | WR | In 80-Column Mode: Double Width Graphics | | ||
| | | CGGA_5E | P | WR | IIc+/Zip Chip: Write: b7 = disable I/O delay, Read: soft switch state | | | | CGGA_5E | P | WR | IIc+/Zip Chip: Write: b7 = disable I/O delay, Read: soft switch state | | ||
| + | | | ZIPGS_5E | G | R | ZipGS: Read last tag and force next write to create trash tag value | | ||
| | C05F 49247 | SETAN3 | OE G | WR | If IOUDIS off: Annunciator 3 On | | | C05F 49247 | SETAN3 | OE G | WR | If IOUDIS off: Annunciator 3 On | | ||
| | | Y0EDGE | C | WR | If IOUDIS on: Interrupt on Y0 Falling | | | | Y0EDGE | C | WR | If IOUDIS on: Interrupt on Y0 Falling | | ||
| | | DHIRESOFF | ECG | WR | In 80-Column Mode: Single Width Graphics | | | | DHIRESOFF | ECG | WR | In 80-Column Mode: Single Width Graphics | | ||
| | | CGGA_5F | P | WR | IIc+/Zip Chip: Paddle delay & Language Card cache | | | | CGGA_5F | P | WR | IIc+/Zip Chip: Paddle delay & Language Card cache | | ||
| + | | | ZIPGS_5F | G | R | ZipGS: Read last tag and reset cshupd | | ||
| + | | C060-C06F | OKI6242 | C | WR | AE Z-RAM Ultra Clock - OKI 6242 chip (low 4 bits of each location) | | ||
| | C060 49248 | TAPEIN | OE | R7 | Read Cassette Input (not on IIe PDS Card) | | | C060 49248 | TAPEIN | OE | R7 | Read Cassette Input (not on IIe PDS Card) | | ||
| - | | | | C | R7 | Status of 80/40 Column Switch | | + | | | | C | R7 | Status of 80/40 Column Switch (not IIc Plus) | |
| | | BUTN3 | G | R7 | Switch Input 3 | | | | BUTN3 | G | R7 | Switch Input 3 | | ||
| | C061 49249 | BUTN0 | OECG | R7 | Switch Input 0 \\ Open Apple/Command (not II/II+) | | | C061 49249 | BUTN0 | OECG | R7 | Switch Input 0 \\ Open Apple/Command (not II/II+) | | ||
| Line 136: | Line 150: | ||
| | | RDMOUY1 | C | R7 | Mouse Vert Position | | | | RDMOUY1 | C | R7 | Mouse Vert Position | | ||
| | C068 49256 | STATEREG | G | V | b0=INTCXROM b1=ROMBANK b2=LCBNK2 b3=RDROM \\ b4=RAMWRT b5=RAMRD b6=PAGE2 b7=ALTZP | | | C068 49256 | STATEREG | G | V | b0=INTCXROM b1=ROMBANK b2=LCBNK2 b3=RDROM \\ b4=RAMWRT b5=RAMRD b6=PAGE2 b7=ALTZP | | ||
| + | | C06A 49258 | FASTCHIP_6A | E | W | FastChip %%//%%e: Lock/Unlock register | | ||
| + | | C06B 49259 | FASTCHIP_6B | E | W | FastChip %%//%%e: Enable other registers | | ||
| + | | | | E | R7 | FastChip %%//%%e: b7=1 Registers enabled | | ||
| + | | C06C 49260 | FASTCHIP_6C | E | V | FastChip %%//%%e: Slot speed register | | ||
| | C06D 49261 | TESTREG | ???? | | Test Mode Bit Register | | | C06D 49261 | TESTREG | ???? | | Test Mode Bit Register | | ||
| + | | | FASTCHIP_6D | E | V | FastChip %%//%%e: Clock speed register | | ||
| | C06E 49262 | CLRTM | ???? | | Clear Test Mode | | | C06E 49262 | CLRTM | ???? | | Clear Test Mode | | ||
| + | | | FASTCHIP_6E | E | V | FastChip %%//%%e: Config register select | | ||
| | C06F 49263 | ENTM | ???? | | Enable Test Mode | | | C06F 49263 | ENTM | ???? | | Enable Test Mode | | ||
| - | | C070 49264 | PTRIG | E | R | Analog Input Reset | | + | | | FASTCHIP_6F | E | V | FastChip %%//%%e: Config register value | |
| + | | C070 49264 | PTRIG | OECG | R | Analog Input Reset | | ||
| | | | C | WR | Analog Input Reset + Reset VBLINT Flag | | | | | C | WR | Analog Input Reset + Reset VBLINT Flag | | ||
| | C071--C07F | | G | | 15 bytes of code for IRQ/BRK handling | | | C071--C07F | | G | | 15 bytes of code for IRQ/BRK handling | | ||
| | C072 49266 | ??? | M | W | IIe PDS Card: [[mg_notes:iie_card:io_addresses|unknown]] | | | C072 49266 | ??? | M | W | IIe PDS Card: [[mg_notes:iie_card:io_addresses|unknown]] | | ||
| | C073 49267 | BANKSEL | EC | W | RAMworks-style Aux RAM Card bank select | | | C073 49267 | BANKSEL | EC | W | RAMworks-style Aux RAM Card bank select | | ||
| + | | C074 49268 | TRANSWARP | OE | W | Transwarp speed: 0 = max speed, 1 = 1 MHz, 3 = disable | | ||
| | C077 49271 | BLOSSOM | | W | Appleblossom Special I/O Address \\ $C1=Install clock driver \\ $CC=Get time in input buffer \\ $CF=get time in ProDOS global page| | | C077 49271 | BLOSSOM | | W | Appleblossom Special I/O Address \\ $C1=Install clock driver \\ $CC=Get time in input buffer \\ $CF=get time in ProDOS global page| | ||
| | C078 49272 | | C | W | Disable IOU Access | | | C078 49272 | | C | W | Disable IOU Access | | ||
| Line 170: | Line 192: | ||
| | C08E 49294 | | OECG | R | Read ROM; no write | | | C08E 49294 | | OECG | R | Read ROM; no write | | ||
| | C08F 49295 | | OECG | RR | Read/write RAM bank 1 | | | C08F 49295 | | OECG | RR | Read/write RAM bank 1 | | ||
| - | | C090--C09F | | OE G | | slot 1 (not IIe PDS Card) | | + | | C090--C09F | | OE G | | slot 1 (virtual in IIe PDS Card) | |
| | C098 | | C | V | ACIA 1 tx/rx data register | | | C098 | | C | V | ACIA 1 tx/rx data register | | ||
| | C099 | | C | V | ACIA 1 tx/rx status register | | | C099 | | C | V | ACIA 1 tx/rx status register | | ||
| | C09A | | C | V | ACIA 1 tx/rx command register | | | C09A | | C | V | ACIA 1 tx/rx command register | | ||
| | C09B | | C | V | ACIA 1 tx/rx control register | | | C09B | | C | V | ACIA 1 tx/rx control register | | ||
| - | | C0A0--C0AF | | OE G | | slot 2 (not IIe PDS Card) | | + | | C0A0--C0AF | | OE G | | slot 2 (virtual in IIe PDS Card) | |
| | C098 | | C | V | ACIA 2 tx/rx data register | | | C098 | | C | V | ACIA 2 tx/rx data register | | ||
| | C099 | | C | V | ACIA 2 tx/rx status register | | | C099 | | C | V | ACIA 2 tx/rx status register | | ||
| | C09A | | C | V | ACIA 2 tx/rx command register | | | C09A | | C | V | ACIA 2 tx/rx command register | | ||
| | C09B | | C | V | ACIA 2 tx/rx control register | | | C09B | | C | V | ACIA 2 tx/rx control register | | ||
| - | | C0B0--C0BF | | OE G | | slot 3 (not IIe PDS Card) | | + | | C0B0--C0BF | | OE G | | slot 3 (video only in IIe PDS Card) | |
| | C0C0--C0CF | | OE G | | slot 4 (not IIe PDS Card) | | | C0C0--C0CF | | OE G | | slot 4 (not IIe PDS Card) | | ||
| | C0C0 | ADDRL | C | V | IIc Mem Expansion: Address low byte | | | C0C0 | ADDRL | C | V | IIc Mem Expansion: Address low byte | | ||
| Line 186: | Line 208: | ||
| | C0C2 | ADDRH | C | V | IIc Mem Expansion: Address high byte | | | C0C2 | ADDRH | C | V | IIc Mem Expansion: Address high byte | | ||
| | C0C3 | DATA | C | V | IIc Mem Expansion: Address data byte | | | C0C3 | DATA | C | V | IIc Mem Expansion: Address data byte | | ||
| - | | C0D0--C0DF | | OE G | | slot 5 (not IIe PDS Card) | | + | | C0D0--C0DF | | OE G | | slot 5 (virtual in IIe PDS Card) | |
| - | | C0E0--C0EF | | OE G | | slot 6 (not IIe PDS Card) | | + | | C0E0--C0EF | | OE G | | slot 6 (Disk II only in IIe PDS Card) | |
| | C0E0 | | MCG | | IWM:PH0 off | | | C0E0 | | MCG | | IWM:PH0 off | | ||
| | C0E1 | | MCG | | IWM:PH0 on | | | C0E1 | | MCG | | IWM:PH0 on | | ||
| Line 204: | Line 226: | ||
| | C0EE | | MCG | | IWM:Q7 off (WP sense/read) | | | C0EE | | MCG | | IWM:Q7 off (WP sense/read) | | ||
| | C0EF | | MCG | | IWM:Q7 on (Write) | | | C0EF | | MCG | | IWM:Q7 on (Write) | | ||
| - | | C0F0--C0FF | | OE G | | slot 7 (not IIe PDS Card) | | + | | C0F0--C0FF | | OE G | | slot 7 (virtual in IIe PDS Card) | |
| + | |||
| + | ===== IIgs Quick Ref Table ===== | ||
| + | |||
| + | Borrowed from [[http://www.txbobsc.com/aal/1987/aal8701.html|here]]. | ||
| + | ^ ^ C02x ^ C03x ^ C04x ^ C05x ^ C06x ^ | ||
| + | ^ 0 | //rsvd// | Speaker | //rsvd// | Graphics | Switch 3 | | ||
| + | ^ 1 | MONO | 3.5 Disk | Mouse Int | Text | Switch 0 | | ||
| + | ^ 2 | TXT Color | Scan Int | //rsvd// | Unmixed | Switch 1 | | ||
| + | ^ 3 | VGC Int | Clock Data | //rsvd// | Mixed | Switch 2 | | ||
| + | ^ 4 | MouseData | Clock Ctrl | M Delta X | Text 1 | Paddle 0 | | ||
| + | ^ 5 | Key Mods | Shadow | M Delta Y | Text 2 | Paddle 1 | | ||
| + | ^ 6 | KM Data | Speed | M Flags | Lo Res | Paddle 2 | | ||
| + | ^ 7 | KM Status | DMA Bank | VBL Int | Hi Res | Paddle 3 | | ||
| + | ^ 8 | ROM Bank | SCC B Cmd | XY Int | Clr AN0 | State Reg | | ||
| + | ^ 9 | New Video | SCC A Cmd | //rsvd// | Set AN0 | //rsvd// | | ||
| + | ^ A | //rsvd// | SCC B Data | //rsvd// | Clr AN1 | //rsvd// | | ||
| + | ^ B | Lang Sel | SCC A Data | //rsvd// | Set AN1 | //rsvd// | | ||
| + | ^ C | CharROM | Sound Ctrl | //rsvd// | Clr AN2 | //rsvd// | | ||
| + | ^ D | Slot ROM | Sound Data | //rsvd// | Set AN2 | Test Mode | | ||
| + | ^ E | Vert Cnt | Sound AdrL | //rsvd// | Clr AN3 | Test Off | | ||
| + | ^ F | Horiz Cnt | Sound AdrH | //rsvd// | Set AN3 | Test On | | ||